Digital systems

The following LOs are achieved by the student by completing the assignment successfully

• Design digital systems using different modeling styles in laboratory;
• Design, implement digital hardware/system on CPLD/FPGA target board and report with the help of literature review working in groups; and
• Outline and defend the analysed data related to the designed system

Assignment Objective
The objective of the assignment is to ensure the achievement of the learning process related to VHDL programming and familiarization with the simulation and board implementation.

Assignment Tasks:
Task 1:
Submit a work proposal (outline) for the below tasks (Task 2-4) on or before 05-11-20 including

• Understanding of deliverables – a detail description of deliverables.
• General overview of proposed plan - initial understanding of solutions& references.
• Timeline for completion of the given tasks.
  The work proposal must be submitted in a word file through the link available in Moodle. (10 Marks)
  Task 2:
  Perform the following experiments in Quartus prime 15.1 software and provide evidence of successful compilation. Each Experiment (answer) should contain
  • Task requirement such as truth table/Boolean equation/ circuit diagram. (2 Marks)
  • Text of the VHDL code. (3 Marks)
  • List out errors and problems encountered during compilation and steps to correct them.
  (2 Marks)
  • Successful Compilation screenshot (evidence) including date & time. (3 Marks)
  • Simulation output in Modelsim with annotation. (5 Marks)

a) Experiment 1: Design a full adder using conditional signal assignment statements in VHDL, compile it using Quartus prime and simulate in Modelsim.
b) Experiment 2: Design a 1:8 De_Multiplexer using direct signal assignment statements in VHDL, compile it using Quartus prime and simulate in Modelsim.
(2×15 Marks=30 Marks)
Task 3:
73180 is a medium scale digital IC working as a 9 bit odd or even parity checker.
a. Perform a literature review(refer at least 2 research papers) on the hardware and obtain details such as (6 Marks)
• Basic operation & implementation of the IC Using VHDL
• Pin diagram
• Brief description (feature & functionality) of all the pins (except VCC and GND)
b. Model the IC as given in Task 3(a) using VHDL in structural style . Write a well-commented VHDL program. (7 Marks)
c. Compile the program in Quartus Prime software (Provide screenshot of compilation as evidence with date) (5 Marks)
d. Write a testbench code for the VHDL program in Task 3(c) and compile & simulate the result in Modelsim (provide the well commented testbench code and screenshot of simulated waveform as evidence). (17 Marks)

Task 4:
Answer the following questions with respect to various digital circuit implementation on FPGA (Field programmable Gate Array) Board.
a. To configure a BCD to seven-segment decoder on DE2-115 target board, how many slide switches and LEDs will you use? Explain with the input output layout. (4 Marks)
b. For the given program segment, the performance of implementation on FPGA board is not as per the expectation, suggest possible options to rectify the mistakes. (6 Marks)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity E1 is port ( A,B: in bit; X: out bit );
end E1;
architecture E11 of E1 is
begin
process(a)
begin
if a=’0’ then x<=’1’;
elsif b=’1’ then x<=’0’;
else x<=’0’;
end if;
end process;
end E11;

c. For the given block diagram in Figure 1, the entity declaration shows some errors, detect the errors and rewrite the code after rectifying the same. (5 Marks)

Figure 1
Entity block is
Port(a,b: in std_logic; d,f,g:out std_logic);
End block;

d. For the given program segment identify the errors and rectify. Give justification. (5 Marks)

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL;
entity and is
port ( A,B,C: in STD_LOGIC; X,Y: out STD_LOGIC );
end and;
architecture E22 of and is
begin
X<=A and B;
Y<= X OR C;
End E22;

e. For the given program segment identify the errors and rectify them . Give Justification. (5 Marks)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity E1 is port ( A: in STD_LOGIC; B: in STD_LOGIC; X: out STD_LOGIC );
end E1;
architecture E1behavior of E1 is
begin
signal S1,S2: std_logic;
process(a,b)
S1< = A and not B;
S2<= not A and B ;
X<= S1 or S2;
wait for 10 ns;
end process;
end E11;

Rules & Regulations:
• All resources should be cited using CU Harvard style.
• The final assignment must have a Title page, References/ bibliography using CU Harvard Style and page numbers.
• Title Page must have Assignment Name, Module name, Session, your name, ID, and the name of the faculty.
• Softcopy in word format is to be submitted through Turnitin link on Moodle.
• The answer should be typed. No images to be kept other than the places where a screenshot is expected in the question.
• Viva will be conducted after the assignment submission as per the dates informed earlier.

Sample Solution