The goal in this project is to implement the MSI cache coherence protocol in Python programming language. How the protocol works and state transitions on the protocol can be found in Lecture 5 slides. Wikipedia also has a nice high level description of the protocol. Consider only one level of cache which is a write back cache. Moreover, assume that there are 4 processing cores working on a single shared memory. To simplify, assume that you are writing the code for only one block of cache and that block can hold 4 different memory locations.
Sample Solution