Implement a single cycle MIPS datapath and then extend it to include subroutine and pipelining capabilities (multi-cycle).
This includes anything from designing with basic blocks, to using VHDL/Verilog black boxes- must ensure that the model works with the Simulink environment provided in Matlab.
1) To design and simulate a simple single-cycle MIPS datapath . All datapath components will be needed, including the control unit and ALU control block which provide the rest of the datapath with control signals. The datapath must be able to implement at least the the instructions: R-type instructions: add, sub, and, or I-type instructions: lw, sw, beq, addi, lui, slti Control flow: bnq, beq, j
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